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LTC3630 1 3630f typical application features description high efficiency, 65v 500ma synchronous step-down converter the ltc ? 3630 is a high efficiency step-down dc/dc converter with internal high side and synchronous power switches that draws only 12a typical dc supply current while maintaining a regulated output voltage at no load. the LTC3630 can supply up to 500ma load current and features a programmable peak current limit that provides a simple method for optimizing efficiency and for reduc- ing output ripple and component size. the LTC3630s combination of burst mode ? operation, integrated power switches, low quiescent current, and programmable peak current limit provides high efficiency over a broad range of load currents. with its wide input range of 4v to 65v, the LTC3630 is a robust converter suited for regulating a wide variety of power sources. additionally, the LTC3630 includes a precise run threshold and soft-start feature to guarantee that the power system start-up is well-controlled in any environ - ment. a feedback comparator output enables multiple LTC3630s to be paralleled in higher current applications. the LTC3630 is available in the thermally-enhanced 3mm 5mm dfn and the mse16 packages. efficiency vs load current 4v to 65v input to 3.3v output, 500ma step-down converter applications n wide operating input voltage range: 4v to 65v n synchronous operation for highest efficiency n internal high side and low side power mosfets n no compensation required n adjustable 50ma to 500ma maximum output current n low dropout operation: 100% duty cycle n low quiescent current: 12a n wide output range: 0.8v to v in n 0.8v 1% feedback voltage reference n precise run pin threshold n internal and external soft-start n programmable 1.8v, 3.3v, 5v or adjustable output n few external components required n low profile (0.75mm) 3mm 5mm dfn and thermally-enhanced mse16 packages n industrial control supplies n medical devices n distributed power systems n portable instruments n battery-operated devices n automotive n avionics l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. sw v in 4v to 65v LTC3630 47h 100f 2 3630 ta01a 2.2f v out 3.3v 500ma gnd v fb ss v prg2 run v prg1 i set fbo v in load current (ma) 50 efficiency (%) 70 90 100 0.1 10 100 1000 3630 ta01b 30 1 80 60 40 v out = 3.3v v in = 12v v in = 65v i set = 220k||220pf i set = open www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 2 3630f absolute maximum ratings v in supply voltage ..................................... C0.3v to 70v sw voltage (dc) ........................... C0.3v to (v in + 0.3v) run voltage ................................................. C0.3v to 6v ss, fbo, i set voltages ................................. C0.3v to 6v v fb , v prg1 , v prg2 voltages ......................... C0.3v to 6v (note 1) 1 3 5 6 7 8 sw v in run v prg2 v prg1 gnd 16 14 12 11 10 9 gnd gnd fbo i set ss v fb top view 17 gnd mse package variation: mse16 (12) 16-lead plastic msop t jmax = 150c, ja = 45c/w, jc = 10c/w exposed pad (pin 17) is gnd, must be soldered to pcb 16 15 14 13 12 11 10 9 17 gnd 1 2 3 4 5 6 7 8 gnd nc gnd nc fbo i set ss v fb sw nc v in nc run v prg2 v prg1 gnd top view dhc package 16-lead (5mm 3mm) plastic dfn (note 6) t jmax = 150c, ja = 43c/w, jc = 5c/w exposed pad (pin 17) is gnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range LTC3630emse#pbf LTC3630emse#trpbf 3630 16-lead plastic msop C40c to 125c LTC3630imse#pbf LTC3630imse#trpbf 3630 16-lead plastic msop C40c to 125c LTC3630hmse#pbf LTC3630hmse#trpbf 3630 16-lead plastic msop C40c to 150c LTC3630mpmse#pbf LTC3630mpmse#trpbf 3630 16-lead plastic msop C55c to 150c LTC3630edhc#pbf LTC3630edhc#trpbf 3630 16-lead (5mm 3mm) plastic dfn C40c to 125c LTC3630idhc#pbf LTC3630idhc#trpbf 3630 16-lead (5mm 3mm) plastic dfn C40c to 125c LTC3630hdhc#pbf LTC3630hdhc#trpbf 3630 16-lead (5mm 3mm) plastic dfn C40c to 150c LTC3630mpdhc#pbf LTC3630mpdhc#trpbf 3630 16-lead (5mm 3mm) plastic dfn C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range (notes 2, 3, 4) LTC3630e, LTC3630i ......................... C40c to 125c LTC3630h .......................................... C40c to 150c LTC3630mp ....................................... C55c to 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) msop ............................................................... 300c www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 3 3630f electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, unless otherwise noted. symbol parameter conditions min typ max units input supply (v in ) v in input voltage operating range 4 65 v v out output voltage operating range 0.8 v in v uvlo v in undervoltage lockout v in rising v in falling hysteresis l l 3.45 3.30 3.65 3.5 150 3.85 3.70 v v mv i q dc supply current (note 5) active mode sleep mode shutdown mode no load v run = 0v 165 12 5 270 20 10 a a a v run run pin threshold voltage run rising run falling hysteresis 1.17 1.06 1.21 1.10 110 1.25 1.14 v v mv output supply (v fb ) v fb(adj) feedback comparator threshold voltage (adjustable output) v fb rising, v prg1 = v prg2 = 0v LTC3630e, LTC3630i LTC3630h, LTC3630mp l l 0.792 0.788 0.800 0.800 0.808 0.812 v v v fbh feedback comparator hysteresis (adjustable output) v fb falling, v prg1 = v prg2 = 0v l 2.5 5 7 mv i fb feedback pin current v fb = 1v, v prg1 = 0v, v prg2 = 0v C10 0 10 na v fb(fixed) feedback comparator threshold voltages (fixed output) v fb rising, v prg1 = ss, v prg2 = 0v v fb falling, v prg1 = ss, v prg2 = 0v l l 4.940 4.910 5.015 4.985 5.090 5.060 v v v fb rising, v prg1 = 0v, v prg2 = ss v fb falling, v prg1 = 0v, v prg2 = ss l l 3.260 3.240 3.310 3.290 3.360 3.340 v v v fb rising, v prg1 = v prg2 = ss v fb falling, v prg1 = v prg2 = ss l l 1.780 1.770 1.810 1.8 1.840 1.83 v v ?v linereg feedback voltage line regulation v in = 4v to 65v 0.001 %/v operation i peak peak current comparator threshold i set floating 100k resistor from i set to gnd i set shorted to gnd l l l 1 0.45 0.09 1.2 0.6 0.12 1.4 0.75 0.15 a a a r on power switch on-resistance top switch bottom switch i sw = C200ma i sw = 200ma 1.00 0.53 i lsw switch pin leakage current run = open, v in = 65v, sw = 0v 0.1 1 a i ss soft-start pin pull-up current v ss < 2.5v 3 5 6 a t int(ss) internal soft-start time ss pin floating 0.8 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3630 is tested under pulsed load conditions such that t j t a . the LTC3630e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3630i is guaranteed over the C40c to 125c operating junction temperature range, the LTC3630h is guaranteed over the C40c to 150c operating junction temperature range and the LTC3630mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja is 43c/w for the dfn or 45c/w for the msop. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 4 3630f typical performance characteristics efficiency and power loss vs load current, v out = 5v efficiency and power loss vs load current, v out = 3.3v efficiency and power loss vs load current, v out = 1.8v soft-start waveform load step transient response short-circuit response electrical characteristics note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 4: this ic includes over temperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. the overtemperature protection level is not production tested. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: for application concerned with pin creepage and clearance distances at high voltages, the msop package should be used. see applications information. output voltage 2v/div inductor current 500ma/div 1ms/div c out = 100f figure 13 circuit 3630 g01 output voltage 50mv/div load current 200ma/div 500s/div v in = 12v v out = 5v figure 13 circuit 3630 g02 output voltage 2v/div inductor current 500ma/div 200s/div v in = 12v v out = 5v figure 13 circuit 3630 g03 load current (ma) 30 efficiency (%) power loss (mw) 90 100 20 10 80 50 70 10 1 100 1000 60 40 0.1 10 100 1000 3630 g04 0 1 efficiency power v out = 5v figure 13 circuit v in = 12v v in = 65v load current (ma) 30 efficiency (%) power loss (mw) 90 100 20 10 80 50 70 10 1 100 1000 60 40 0.1 10 100 1000 3630 g05 0 1 efficiency power v out = 3.3v figure 13 circuit v in = 12v v in = 65v load current (ma) 30 efficiency (%) power loss (mw) 90 100 20 10 80 50 70 10 1 100 1000 60 40 0.1 10 100 1000 3630 g06 0 1 efficiency power v out = 1.8v figure 13 circuit v in = 12v v in = 65v www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 5 3630f typical performance characteristics feedback comparator trip voltage vs temperature feedback comparator hysteresis vs temperature peak current trip threshold vs temperature and i set peak current trip threshold vs r iset peak current trip threshold vs input voltage quiescent v in supply current vs input voltage efficiency vs input voltage line regulation vs input voltage load regulation vs load current input voltage (v) 10 efficiency (%) 70 75 80 40 60 3630 g07 65 60 55 20 30 50 85 90 95 i load = 500ma i load = 100ma i load = 10ma i load = 1ma v out = 5v figure 13 circuit input voltage (v) 5 ?0.05 ?v out /v out (%) ?0.03 ?0.01 0.01 15 25 35 45 3630 g08 55 0.03 0.05 ?0.04 ?0.02 0 0.02 0.04 65 figure 13 circuit i load = 500ma load current (ma) 0 output voltage (v) 4.99 5.00 5.01 300 500 3630 g09 4.98 4.97 4.96 100 200 400 5.02 5.03 5.04 v in = 12v v out = 5v figure 13 circuit temperature (c) ?55 0.796 feedback comparator trip voltage (v) 0.798 0.800 0.802 0.804 ?25 5 35 65 3630 g10 95 125 155 v in = 12v temperature (c) ?55 4.5 feedback comparator hysteresis (mv) 4.6 4.8 4.9 5.0 5.5 5.2 5 65 95 125 3630 g11 4.7 5.3 5.4 5.1 ?25 35 155 v in = 12v temperature (c) ?55 peak current trip threshold (ma) 600 1000 155 3630 g12 400 0 5 65 ?25 35 95 125 v in = 12v 800 200 1200 1400 i set open i set = gnd r iset = 100k r iset (k) 0 1000 1200 1400 200 3630 g13 800 600 50 100 150 250 400 200 0 peak current trip threshold (ma) v in = 12v input voltage (v) 0 800 1000 1400 30 50 3630 g14 600 400 10 20 40 60 200 0 1200 peak current trip threshold (ma) i set = open i set = 100k i set = 0v v in voltage (v) 5 v in supply current (a) 6 8 10 3630 g15 4 2 0 25 45 15 35 55 12 14 16 65 sleep shutdown www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 6 3630f typical performance characteristics switch leakage current vs temperature run comparator threshold voltage vs temperature operating waveforms quiescent v in supply current vs temperature switch on-resistance vs input voltage switch on-resistance vs temperature temperature (c) ?55 ?25 0 v in supply current (a) 8 20 5 65 95 3630 g16 4 16 12 35 125 155 v in = 12v sleep shutdown input voltage (v) 0 0 switch on-resistance () 0.2 0.6 0.8 1.0 2.0 1.4 20 40 top 50 3630 g17 0.4 1.6 1.8 1.2 10 30 60 bottom temperature (c) ?55 switch on-resistance () 1.4 35 3630 g18 0.8 0.4 ?25 5 65 0.2 0 1.6 1.2 1.0 0.6 95 125 155 v in = 12v top bottom temperature (c) ?55 switch leakage current (a) 10 35 3630 g19 4 0 ?25 5 65 ?2 ?4 ?6 14 12 8 6 2 95 125 155 v in = 65v sw = 65v sw = 0v temperature (c) ?55 run comparator threshold (v) 1.20 1.25 1.30 35 95 lt1027 ? 3630 g20 1.15 1.10 ?25 5 65 125 155 1.05 1.00 rising falling output voltage 50mv/div switch voltage 25v/div inductor current 500ma/div 10s/div v in = 65v v out = 5v i load = 350ma figure 13 circuit 3630 g21 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 7 3630f pin functions sw (pin 1): switch node connection to inductor. this pin connects to the drains of the internal power mosfet switches. nc (pins 2, 4, 13, 15 dhc package only): no internal connection. leave these pins open. v in (pin 3): main input supply pin. a ceramic bypass capacitor should be tied between this pin and gnd. run (pin 5): run control input. a voltage on this pin above 1.21v enables normal operation. forcing this pin below 0.7v shuts down the LTC3630, reducing quiescent current to approximately 5a. optionally, connect to the input supply through a resistor divider to set the under - voltage lockout. an internal 2m resistor and 2a current source pulls this pin up to an internal 5v reference. see applications information. v prg2 , v prg1 (pins 6, 7): output voltage selection. short both pins to ground for an external resistive divider pro - grammable output voltage. short v prg1 to ss and short v prg2 to ground for a 5v output voltage. short v prg1 to ground and short v prg2 to ss for a 3.3v output voltage. short both pins to ss for a 1.8v output voltage. gnd (pins 8, 14, 16, exposed pad pin 17): ground. the exposed backside pad must be soldered to the pcb ground plane for optimal thermal performance. v fb (pin 9): output voltage feedback. when configured for an adjustable output voltage, connect to an external resistive divider to divide the output voltage down for comparison to the 0.8v reference. for the fixed output configuration, directly connect this pin to the output supply. ss (pin 10): soft-start control input. a capacitor to ground at this pin sets the output voltage ramp time. a 50a current initially charges the soft-start capacitor until switching begins, at which time the current is reduced to its nominal value of 5a. the output voltage ramp time from zero to its regulated value is 1ms for every 16.5nf of capacitance from ss to gnd. if left floating, the ramp time defaults to an internal 0.8ms soft-start. i set (pin 11): peak current set input and voltage output ripple filter. a resistor from this pin to ground sets the peak current comparator threshold. leave floating for the maximum peak current (1.2a typical) or short to ground for minimum peak current (0.12a typical). the maximum output current is one-half the peak current. the 5a current that is sourced out of this pin when switching, is reduced to 1a in sleep. optionally, a capacitor can be placed from this pin to gnd to trade off efficiency for light load output voltage ripple. see applications information. fbo (pin 12): feedback comparator output. connect to the v fb pins of additional LTC3630s to combine the output current. the typical pull-up current is 20a. the typical pull- down impedance is 70. see applications information. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 8 3630f block diagram c out c in v out + ? + ? + 3 ? + ? + + peak current comparator reverse current comparator feedback comparator voltage reference v prg2 gnd gnd ss ss v prg1 gnd ss gnd ss r1 1.0m 4.2m 2.5m 1.0m r2 800k 800k 800k v out adjustable 5v fixed 3.3v fixed 1.8v fixed start-up: 50a normal: 5a implement divider externally for adjustable version v in v in 1 sw l1 gnd logic and shoot- through prevention 16 ss r2 r1 5v 5v 20a fbo 70 10 12 gnd 8 14 gnd 17 v fb 9 v prg1 7 v prg2 3630 bd 6 0.800v 1.21v run 2m 5v i set 11 active: 5a sleep: 1a sleep, active: 2a shutdown: 0a 1.3v 5 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 9 3630f operation the LTC3630 is a synchronous step-down dc/dc con - verter with internal power switches that uses burst mode control. the low quiescent current and high switching frequency results in high efficiency across a wide range of load currents. burst mode operation functions by using short burst cycles to switch the inductor current through the internal power mosfets, followed by a sleep cycle where the power switches are off and the load current is supplied by the output capacitor. during the sleep cycle, the LTC3630 draws only 12a of supply current. at light loads, the burst cycles are a small percentage of the total cycle time which minimizes the average supply current, greatly improving efficiency. figure 1 shows an example of burst mode operation. the switching frequency and the number of switching cycles during burst mode operation are dependent on the inductor value, peak current, load current, input voltage and output voltage. reference, the comparator activates a sleep mode in which the power switches and current comparators are disabled, reducing the v in pin supply current to only 12a. as the load current discharges the output capacitor, the voltage on the v fb pin decreases. when this voltage falls 5mv below the 800mv reference, the feedback comparator trips and enables burst cycles. at the beginning of the burst cycle, the internal high side power switch (p-channel mosfet) is turned on and the inductor current begins to ramp up. the inductor current increases until either the current exceeds the peak cur - rent comparator threshold or the voltage on the v fb pin exceeds 800mv, at which time the high side power switch is turned off and the low side power switch (n-channel mosfet) turns on. the inductor current ramps down until the reverse current comparator trips, signaling that the current is close to zero. if the voltage on the v fb pin is still less than the 800mv reference, the high side power switch is turned on again and another cycle commences. the average current during a burst cycle will normally be greater than the average load current. for this architecture, the maximum average output current is equal to half of the peak current. the hysteretic nature of this control architecture results in a switching frequency that is a function of the input voltage, output voltage, and inductor value. this behavior provides inherent short-circuit protection. if the output is shorted to ground, the inductor current will decay very slowly during a single switching cycle. since the high side switch turns on only when the inductor current is near zero, the LTC3630 inherently switches at a lower frequency during start-up or short-circuit conditions. start-up and shutdown if the voltage on the run pin is less than 0.7v, the LTC3630 enters a shutdown mode in which all internal circuitry is disabled, reducing the dc supply current to 5a. when the voltage on the run pin exceeds 1.21v, normal operation of the main control loop is enabled. the run pin com - parator has 110mv of internal hysteresis, and therefore must fall below 1.1v to stop switching and disable the main control loop. burst frequency inductor current output voltage ?v out 3630 f01 burst cycle sleep cycle switching frequency figure 1. burst mode operation main control loop the LTC3630 uses the v prg1 and v prg2 control pins to connect internal feedback resistors to the v fb pin. this enables fixed outputs of 1.8v, 3.3v or 5v without increas - ing component count, input supply current or exposure to noise on the sensitive input to the feedback comparator. external feedback resistors (adjustable mode) can still be used by connecting both v prg1 and v prg2 to ground. in adjustable mode the feedback comparator monitors the voltage on the v fb pin and compares it to an inter - nal 800mv reference. if this voltage is greater than the (refer to block diagram) www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 10 3630f an internal 0.8ms soft-start function limits the ramp rate of the output voltage on start-up to prevent excessive input supply droop. if a longer ramp time and consequently less supply droop is desired, a capacitor can be placed from the ss pin to ground. the 5a current that is sourced out of this pin will create a smooth voltage ramp on the capacitor. if this ramp rate is slower than the internal 0.8ms soft-start, then the output voltage will be limited by the ramp rate on the ss pin instead. the internal and external soft-start functions are reset on start-up and after an undervoltage event on the input supply. the peak inductor current is not limited by the internal or external soft-start functions; however, placing a capacitor from the i set pin to ground does provide this capability. peak inductor current programming the peak current comparator nominally limits the peak inductor current to 1.2a. this peak inductor current can be adjusted by placing a resistor from the i set pin to ground. the 5a current sourced out of this pin through the resistor generates a voltage that adjusts the peak cur - rent comparator threshold. during sleep mode, the current sourced out of the i set pin is reduced to 1a. the i set current is increased back to 5a on the first switching cycle after exiting sleep mode. the i set current reduction in sleep mode, along with adding a filtering capacitor, c iset , from the i set pin to ground, provides a method of reducing light load output voltage ripple at the expense of lower efficiency and slightly de - graded load step transient response. for applications requiring higher output current, the LTC3630 provides a feedback comparator output pin (fbo) for combining the output current of multiple LTC3630s. by connecting the fbo pin of a master LTC3630 to the v fb pin of one or more slave LTC3630s, the output currents can be combined to source much more than 500ma. operation dropout operation when the input supply decreases toward the output sup - ply, the duty cycle increases to maintain regulation. the p-channel mosfet top switch in the LTC3630 allows the duty cycle to increase all the way to 100%. at 100% duty cycle, the p-channel mosfet stays on continuously, pro - viding output current equal to the peak current, which can be greater than 1a. the power dissipation of the LTC3630 can increase dramatically during dropout operation espe - cially at input voltages less than 10v. the increased power dissipation is due to higher potential output current and increased p-channel mosfet on-resistance. see the ther - mal considerations section of the applications information for a detailed example. input voltage and overtemperature protection when using the LTC3630, care must be taken not to exceed any of the ratings specified in the absolute maxi- mum ratings section. as an added safeguard, however, the LTC3630 incorporates an overtemperature shutdown feature. if the junction temperature reaches approximately 180c, the LTC3630 will enter thermal shutdown mode. both power switches will be turned off and the sw node will become high impedance. after the part has cooled below 160c, it will restart. the overtemperature level is not production tested. the LTC3630 can provide a programmable undervoltage lockout which can also serve as a precise input voltage monitor by using a resistive divider from v in to gnd with the tap connected to the run pin. switching is enabled when the run pin voltage exceeds 1.21v and is disabled when dropping below 1.1v. pulling the run pin below 700mv forces a low quiescent current shutdown (5a). furthermore, if the input voltage falls below 3.5v typi- cal (3.7v maximum), an internal undervoltage detector disables switching. when switching is disabled, the LTC3630 can safely sus - tain input voltages up to the absolute maximum rating of 70v. input supply undervoltage events trigger a soft-start reset, which results in a graceful recovery from an input supply transient. (refer to block diagram) www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 11 3630f applications information the basic LTC3630 application circuit is shown on the front page of the data sheet. external component selection is determined by the maximum load current requirement and begins with the selection of the peak current programming resistor, r iset . the inductor value l can then be determined, followed by capacitors c in and c out . peak current resistor selection the peak current comparator has a guaranteed maximum current limit of 1a (1.2a typical), which guarantees a maximum average current of 500ma. for applications that demand less current, the peak current threshold can be reduced to as little as 100ma (120ma typical). this lower peak current allows the use of lower value, smaller components (input capacitor, output capacitor, and induc - tor), resulting in lower input supply ripple and a smaller overall dc/dc converter. the threshold can be easily programmed using a resis- tor (r iset ) between the i set pin and ground. the voltage generated on the i set pin by r iset and the internal 5a current source sets the peak current. the voltage on the i set pin is internally limited within the range of 0.1v to 1.0v. the value of resistor for a particular peak current can be selected by using figure 2 or the following equation: r iset = i peak ? 0.2 ? 10 6 where 100ma < i peak < 1a. the internal 5a current source is reduced to 1a in sleep mode to maximize efficiency and to facilitate a trade-off between efficiency and light load output voltage ripple, as described in the c iset selection section of the applica - tions information. for maximum efficiency, minimize the capacitance on the i set pin and place the r iset resistor as close to the pin as possible. the typical peak current is internally limited to be within the range of 120ma to 1.2a. shorting the i set pin to ground programs the current limit to 120ma, and leaving it float sets the current limit to the maximum value of 1.2a. when selecting this resistor value, be aware that the maximum average output current for this architecture is limited to half of the peak current. therefore, be sure to select a value that sets the peak current with enough margin to provide adequate load current under all conditions. selecting the peak current to be 2.2 times greater than the maximum load current is a good starting point for most applications. inductor selection the inductor, input voltage, output voltage, and peak cur - rent determine the switching frequency during a burst cycle of the LTC3630. for a given input voltage, output voltage, and peak current, the inductor value sets the switching frequency during a burst cycle when the output is in regulation. generally, switching between 50khz and 250khz yields high efficiency, and 200khz is a good first choice for many applications. the inductor value can be determined by the following equation: l = v out f ? i peak ? ? ? ? ? ? ? 1? v out v in ? ? ? ? ? ? the variation in switching frequency during a burst cycle with input voltage and inductance is shown in figure 3. for lower values of i peak , multiply the frequency in figure?3 by 1.2a/i peak . an additional constraint on the inductor value is the LTC3630s 150ns minimum on-time of the high side switch. therefore, in order to keep the current in the inductor well- controlled, the inductor value must be chosen so that it is larger than a minimum value which can be computed as follows: l > v in(max) ? t on(min) i peak ? 1.2 figure 2. r iset selection maximum load current (ma) 50 r iset (k) 60 180 200 220 150 250 300 350 3630 f02 20 140 100 40 160 0 120 80 100 200 400 450 500 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 12 3630f applications information where v in(max) is the maximum input supply voltage when switching is enabled, t on(min) is 150ns, i peak is the peak current, and the factor of 1.2 accounts for typical inductor tolerance and variation over temperature. inductor values that violate the above equation will cause the peak current to overshoot and permanent damage to the part may occur. although the above equation provides the minimum in - ductor value, higher efficiency is generally achieved with a larger inductor value, which produces a lower switching frequency. the inductor value chosen should also be large enough to keep the inductor current from going very nega - tive which is more of a concern at higher v out (>~12v). for a given inductor type, however, as inductance is increased, dc resistance (dcr) also increases. higher dcr trans- lates into higher copper losses and lower current rating, both of which place an upper limit on the inductance. the recommended range of inductor values for small surface mount inductors as a function of peak current is shown in figure 4. the values in this range are a good compromise between the trade-offs discussed above. for applications where board area is not a limiting factor, inductors with larger cores can be used, which extends the recommended range of figure?4 to larger values. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of the more expensive ferrite cores. actual core loss is independent of core size for a fixed inductor value but is very dependent of the inductance selected. as the inductance increases, core losses decrease. un - fortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura - tion. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequently output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy but generally cost more than powdered iron core inductors with similar charac - teristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, tdk, toko, and sumida. c in and c out selection the input capacitor, c in , is needed to filter the trapezoidal current at the source of the top high side mosfet. c in should be sized to provide the energy required to charge figure 4. recommended inductor values for maximum efficiency figure 3. switching frequency for v out = 3.3v v in input voltage (v) 0 switching frequency (khz) 400 500 600 60 3630 f03 300 200 0 10 20 30 40 50 100 v out = 3.3v i set open l = 4.2h l = 10h l = 22h l = 47h l = 100h peak inductor current (ma) 100 10 inductor value (h) 100 1000 1000 3630 f04 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 13 3630f applications information the inductor without causing a large decrease in input voltage ( ?v in ). the relationship between c in and ?v in is given by: c in > l ? i peak 2 2 ? v in ? ? v in it is recommended to use a larger value for c in than calculated by the above equation since capacitance de- creases with applied voltage. in general, a 4.7f x7r ceramic capacitor is a good choice for c in in most LTC3630 applications. to minimize large ripple voltage, a low esr input capaci - tor sized for the maximum rms current should be used. rms current is given by: i rms = i out(max) ? v out v in ? v in v out ? 1 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based only on 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the output capacitor, c out , filters the inductors ripple current and stores energy to satisfy the load current when the LTC3630 is in sleep. the output ripple has a lower limit of v out /160 due to the 5mv typical hysteresis of the feed - back comparator. the time delay of the comparator adds an additional ripple voltage that is a function of the load current. during this delay time, the LTC3630 continues to switch and supply current to the output. the output ripple can be approximated by: ? v out i peak 2 ?i load ? ? ? ? ? ? ? 4 ? 10 ?6 c out + v out 160 the output ripple is a maximum at no load and approaches lower limit of v out /160 at full load. choose the output capacitor c out to limit the output voltage ripple ?v out using the following equation: c out i peak ? 2 ? 10 ?6 ? v out ? v out 160 the value of the output capacitor must be large enough to accept the energy stored in the inductor without a large change in output voltage during a single switching cycle. setting this voltage step equal to 1% of the output voltage, the output capacitor must be: c out > 50 ? l ? i peak v out ? ? ? ? ? ? 2 typically, a capacitor that satisfies the voltage ripple re - quirement is adequate to filter the inductor ripple. to avoid overheating, the output capacitor must also be sized to handle the ripple current generated by the inductor. the worst-case ripple current in the output capacitor is given by i rms = i peak /2. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important only to use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long- term reliability. ceramic capacitors have excellent low esr characteristics but can have high voltage coefficient and audible piezoelectric effects. the high quality factor (q) of ceramic capacitors in series with trace inductance can also lead to significant input voltage ringing. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 14 3630f applications information ceramic capacitors and audible noise higher value, lower cost ceramic capacitors are now be- coming available in smaller case sizes. their high ripple current, high voltage rating, and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for application with inductive source impedance, such as a long wire, an electrolytic capacitor or a ceramic capacitor with a series resistor may be required in parallel with c in to dampen the ringing of the input supply. figure 5 shows this circuit and the typical values required to dampen the ringing. ceramic capacitors are also piezoelectric sensitive. the LTC3630s burst frequency depends on the load current, and in some applications at light load the LTC3630 can excite the ceramic capacitor at audio frequencies, gen - erating audible noise. if the noise is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. connect v prg1 to gnd and v prg2 to ss. for 1.8v, connect both v prg1 and v prg2 to ss. for any of the fixed output voltage options, directly connect the v fb pin to v out . for the adjustable output mode (v prg1 = 0v, v prg2 = 0v), the output voltage is set by an external resistive divider according to the following equation: v out = 0.8v ? 1 + r1 r2 ? ? ? ? ? ? the resistive divider allows the v fb pin to sense a fraction of the output voltage as shown in figure 6. the output voltage can range from 0.8v to v in . be careful to keep the divider resistors very close to the v fb pin to minimize the trace length and noise pick-up on the sensitive v fb signal. r = l in c in 4 ? c in c in l in 3630 f05 v in LTC3630 figure 5. series rc to reduce v in ringing v fb v out r2 3630 f06 0.8v r1 v prg1 v prg2 LTC3630 figure 6. setting the output voltage with external resistors output voltage programming the LTC3630 has three fixed output voltage modes that can be selected with the v prg1 and v prg2 pins and an adjustable mode. the fixed output modes use an internal feedback divider which enables higher efficiency, higher noise immunity, and lower output voltage ripple for 5v, 3.3v and 1.8v applications. to select the fixed 5v output voltage, connect v prg1 to ss and v prg2 to gnd. for 3.3v, to minimize the no-load supply current, resistor values in the megohm range may be used; however, large resistor values should be used with caution. the feedback divider is the only load current when in shutdown. if pcb leakage current to the output node or switch node exceeds the load current, the output voltage will be pulled up. in normal operation, this is generally a minor concern since the load current is much greater than the leakage. to avoid excessively large values of r1 in high output volt - age applications (v out 10v), a combination of external and internal resistors can be used to set the output volt - age. this has an additional benefit of increasing the noise immunity on the v fb pin. figure 7 shows the LTC3630 with the v fb pin configured for a 5v fixed output with an external divider to generate a higher output voltage. the internal 5m resistance appears in parallel with r2, and the value of r2 must be adjusted accordingly. r2 should be chosen to be less than 200k to keep the output voltage variation less than 1% due to the tolerance of the LTC3630s internal resistor. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 15 3630f applications information run pin and external input undervoltage lockout the run pin has two different threshold voltage levels. pulling the run pin below 0.7v puts the LTC3630 into a low quiescent current shutdown mode (i q ~ 5a). when the run pin is greater than 1.21v, the controller is enabled. figure 8 shows examples of configurations for driving the run pin from logic. the current that flows through the r3-r4 divider will directly add to the shutdown, sleep, and active current of the LTC3630, and care should be taken to minimize the impact of this current on the overall efficiency of the application circuit. to keep the variation of the rising v in uvlo threshold to less than 5% due to the internal pull- up circuitry, the following equations should be used to calculate r3 and r4: r3 risingv in uvlothreshold 40a r4 = r3 ? 1.21v risingv in uvlothreshold? 1.21v + r3 ? 4a the falling uvlo threshold will be about 10% lower than the rising v in uvlo threshold due to the 110mv hysteresis of the run comparator. for applications that do not require a precise uvlo, the run pin can be left floating. in this configuration, the uvlo threshold is limited to the internal v in uvlo thresholds as shown in the electrical characteristics table. be aware that the run pin cannot be allowed to exceed its absolute maximum rating of 6v. to keep the voltage on the run pin from exceeding 6v, the following relation should be satisfied: v in(max) < 4.5 ? rising v in uvlo threshold to support a v in(max) greater than 4.5x the external uvlo threshold, an external 4.7v zener diode should be used in parallel with r4. see figure 11. soft-start soft-start is implemented by ramping the effective refer - ence voltage from 0v to 0.8v. to increase the duration of soft-start, place a capacitor from the ss pin to ground. an internal 5a pull-up current will charge this capacitor. the value of the soft-start capacitor can be calculated by the following equation: c ss = soft-start time ? 5a 0.35v 4.2m r1 5v r2 3630 f07 v out 800k 0.8v v fb ss v prg1 v prg2 LTC3630 figure 7. setting the output voltage with external and internal resistors run supply LTC3630 run 3630 f08 LTC3630 figure 8. run pin interface to logic figure 9. adjustable uv lockout run 5v 2m sleep, active: 2a shutdown: 0a 3630 f09 r3 v in LTC3630 r4 the run pin can alternatively be configured as a precise undervoltage (uvlo) lockout on the v in supply with a resistive divider from v in to ground. a simple resistive divider can be used as shown in figure 9 to meet specific v in voltage requirements. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 16 3630f applications information the minimum soft-start time is limited to the internal soft- start timer of 0.8ms. when the LTC3630 detects a fault condition (input supply undervoltage or overtemperature) or when the run pin falls below 1.1v, the ss pin is quickly pulled to ground and the internal soft-start timer is reset. this ensures an orderly restart when using an external soft-start capacitor. note that the soft-start capacitor may not be the limiting factor in the output voltage ramp. the maximum output current, which is equal to half the peak current, must charge the output capacitor from 0v to its regulated value. for small peak currents or large output capacitors, this ramp time can be significant. therefore, the output voltage ramp time from 0v to the regulated v out value is limited to a minimum of: ramp time 2 ? c out i peak v out c iset selection once the peak current resistor, r iset , and inductor are se- lected to meet the load current and frequency requirements, an optional capacitor, c iset , can be added in parallel with r iset . this will boost efficiency at mid-loads and reduce the output voltage ripple dependency on load current at the expense of slightly degraded load step transient response. the peak inductor current is controlled by the voltage on the i set pin. current out of the i set pin is 5a while the LTC3630 is switching and is reduced to 1a during sleep mode. the i set current will return to 5a on the first cycle after sleep mode. placing a parallel rc from the i set pin to ground filters the i set voltage as the LTC3630 enters and exits sleep mode which in turn will affect the output volt - age ripple, efficiency and load step transient performance. in general, when r iset is greater than 120k a c iset ca - pacitor in the 100pf to 200pf range will improve most performance parameters. when r iset is less than 100k, the capacitance on the i set pin should be minimized. higher current applications for applications that require more than 500ma, the LTC3630 provides a feedback comparator output pin v fb sw l1 l2 v in run r3 c in c out v out 5v 1a c ss v in r4 ss v prg1 v prg2 fbo LTC3630 (master) sw v fb v in run ss v prg1 v prg2 fbo 3630 f10 LTC3630 (slave) i set i set figure 10. 5v, 1a regulator (fbo) for driving additional LTC3630s. when the fbo pin of a master LTC3630 is connected to the v fb pin of one or more slave LTC3630s, the master controls the burst cycle of the slaves. figure 10 shows an example of a 5v, 1a regulator using two LTC3630s. the master is configured for a 5v fixed output with external soft-start and the v in uvlo level is set by the run pin. since the slaves are directly controlled by the master, the ss pin of the slave should have minimal capacitance and the run pin of the slave should be floating. furthermore, slaves should be configured for a 1.8v fixed output (v prg1 = v prg2 = ss) to set the v fb pin threshold at 1.8v. the inductors l1 and l2 do not necessarily have to be the same, but should both meet the criteria described above in the inductor selection section. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 17 3630f applications information although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in operating current and i 2 r losses. the v in operating current dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. 1. the v in operating current comprises two components: the dc supply current as given in the electrical charac - teristics and the internal mosfet gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge, ?q, moves from v in to ground. the resulting ?q/dt is the current out of v in that is typically larger than the dc bias current. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor r l . when switching, the average output current flowing through the inductor is chopped between the high side pmos switch and the low side nmos switch. thus, the series resistance looking back into the switch pin is a function of the top and bottom switch r ds(on) values and the duty cycle (dc = v out /v in ) as follows: r sw = (r ds(on)top )dc + (r ds(on)bot ) ? (1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteris - tics curves. thus, to obtain the i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current: i 2 r loss = i o 2 (r sw + r l ) other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% of the total power loss. thermal considerations in most applications, the LTC3630 does not dissipate much heat due to its high efficiency. but, in applications where the LTC3630 is running at high ambient temperature with low supply voltage and high duty cycles, such as dropout, the heat dissipated may exceed the maximum junction temperature of the part. to prevent the LTC3630 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junc - tion temperature of the part. the temperature rise from ambient to junction is given by: t r = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature is given by: t j = t a + t r generally, the worst-case power dissipation is in dropout at low input voltage. in dropout, the LTC3630 can provide a dc current as high as the full 1.2a peak current to the output. at low input voltage, this current flows through a higher resistance mosfet, which dissipates more power. as an example, consider the LTC3630 in dropout at an input voltage of 5v, a load current of 500ma and an ambient temperature of 85c. from the typical performance graphs of switch on-resistance, the r ds(on) of the top switch at v in = 5v and 100c is approximately 1.9. therefore, the power dissipated by the part is: p d = (i load ) 2 ? r ds(on) = (500ma) 2 ? 1.9 = 0.475w for the msop package the ja is 45c/w. thus, the junc - tion temperature of the regulator is: t j = 85 c + 0.475w ? 45 c w = 106.4 c which is below the maximum junction temperature of 150c. note that the while the LTC3630 is in dropout, it can provide output current that is equal to the peak current of the part. this can increase the chip power dissipation dramatically and may cause the internal overtemperature protection circuitry to trigger at 180c and shut down the LTC3630. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 18 3630f applications information design example as a design example, consider using the LTC3630 in an application with the following specifications: v in = 24v, v in(max) = 70v, v out = 3.3v, i out = 500ma, f = 200khz. furthermore, assume for this example that switching should start when v in is greater than 12v. first, calculate the inductor value that gives the required switching frequency: l = 3.3v 200khz ? 1.2a ? ? ? ? ? ? ? 1? 3.3v 24v ? ? ? ? ? ? ? 10h next, verify that this value meets the l min requirement. for this input voltage and peak current, the minimum inductor value is: l min = 24v ? 150ns 1.2a ? 3h therefore, the minimum inductor requirement is satisfied and the 10h inductor value may be used. next, c in and c out are selected. for this design, c in should be sized for a current rating of at least: i rms = 500ma ? 3.3v 24v ? 24v 3.3v ? 1 ? 175ma rms the value of c in is selected to keep the input from droop - ing less than 240mv (1%): c in > 10h ? 1.2a 2 2 ? 24v ? 240mv ? 2.2f c out will be selected based on a value large enough to satisfy the output voltage ripple requirement. for a 50mv output ripple, the value of the output capacitor can be calculated from: c out > 10h ? 1.2a 2 2 ? 3.3v ? 50mv ? 47f c out also needs an esr that will satisfy the output voltage ripple requirement. the required esr can be calculated from: esr < 50mv 1.2a ? 40m ? a 47f ceramic capacitor has significantly less esr than 40m. since an output voltage of 3.3v is one of the standard output configurations, the LTC3630 can be configured by connecting v prg1 to ground and v prg2 to the ss pin. the undervoltage lockout requirement on v in can be satis- fied with a resistive divider from v in to the run pin (refer to figure 9). calculate r3 and r4 as follows: r3 = 200k which is 12v 40a r4 = 200k ? 1.21v 12v ? 1.21v + 200k ? 4a = 20.9k choose standard values for r3 = 200k, r4 = 21k. note that the v in falling threshold will be 10% less than the rising threshold or 11v. since the maximum v in is more than 4.5x the uvlo thresh - old, a 4.7v zener diode in parallel with r4 is required to keep the maximum voltage on the run pin less than the absolute maximum of 6v. the i set pin should be left open in this example to select maximum peak current (1.2a typical). figure 11 shows a complete schematic for this design example. v fb sw 10h v in run 200k 2.2f 47f v out 3.3v 500ma v in 24v 21k 4.7v 3630 f11 ss v prg2 v prg1 fbo i set gnd LTC3630 figure 11. 24v to 3.3v, 500ma regulator at 200khz www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 19 3630f applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3630. check the following in your layout: 1. large switched currents flow in the power switches and input capacitor. the loop formed by these compo - nents should be as small as possible. a ground plane is recommended to minimize ground impedance. 2. connect the (+) terminal of the input capacitor, c in , as close as possible to the v in pin. this capacitor provides the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small signal nodes. the rapid transitions on the switching node can couple to high impedance nodes, in particular v fb , and create increased output ripple. 4. flood all unused area on all layers with copper except for the area under the inductor. flooding with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (v in , v out , gnd, or any other dc rail in your system). pin clearance/creepage considerations the LTC3630 is available in two packages (mse16 and dhc) both with identical functionality. however, the 0.2mm (minimum space) between pins and paddle on the dhc - package may not provide sufficient pc board trace clearance between high and low voltage pins in some higher voltage applications. in applications where clearance is required, the mse16 package should be used. the mse16 package has removed pins between all the adjacent high voltage and low voltage pins, providing 0.657mm clearance which will be sufficient for most applications. for more informa - tion, refer to the printed circuit board design standards described in ipc-2221 (www.ipc.org). v fb i set sw l1 v in run r3 r1 r2 c in c out v out v in r4 r iset c iset c ss 3630 f12 fbo ss v prg2 v prg1 LTC3630 vias to ground plane outline of local ground plane v out v in gnd gnd l1 c out c in figure 12. example pcb layout v fb i set sw l1 33h v in run fbo c out 100f 2 c in 4.7f c iset 100pf r iset 220k c in : tdk c5750x7r2a-475m (2220) c out : 2 avx 1812d107mat l1: sumida cdrh105rnp-330n v out 5v 500ma v in 5v to 65v 3630 f13 ss v prg1 v prg2 gnd LTC3630 figure 13. 5v to 65v input to 5v output, high efficiency, 500ma regulator www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 20 3630f typical applications v fb i set sw l1 10h v in run c out 10f c in 2.2f c ss 100nf r iset 100k c in : murata grm42-2x7r225k25d500 c out : kemet c1206c206k9pac l1: vishay ihlp2020bz-100m-11 v out 3.3v 250ma v in 4v to 24v 3630 ta02a fbo ss v prg1 v prg2 gnd LTC3630 4v to 24v input to 3.3v output, 250ma regulator with external soft-start, small size 4v to 53v input to C12v output, positive-to-negative converter efficiency and power loss vs load current maximum load current vs input voltage load current (ma) 30 efficiency (%) power loss (mw) 90 100 20 10 80 50 70 10 1 0 100 1000 60 40 0.1 10 100 3630 ta02b 0 1 efficiency power v out = 3.3v input voltage (v) 5 0 maximum load current (ma) 100 300 400 500 15 25 30 50 3630 ta03b 200 10 20 35 40 45 v out = ?12v v fb sw l1 22h v in run i set fbo c out 22f r1 200k c in 4.7f 100v c in : kemet c1210c475k5rac c out : tdk c4532x7r1c226m l1: coilcraft mss1048-223ml v out ?12v v in 4v to 53v 3630 ta03a ss v prg2 v prg1 gnd LTC3630 r2 147k www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 21 3630f typical applications 12v to 65v input to 36v output with 100ma input current limit maximum input and load current vs input voltage 5v to 65v input to 5v output,150ma regulator with 20khz minimum burst frequency burst frequency vs load current v fb sw l1 33h v in run i set fbo c in 2.2f c out 10f v out 5v 150ma v in 5v to 65v ss v prg1 v prg2 gnd LTC3630 out in div v + set ltc6994-1 gnd r iset 60.4k 30.1 3630 ta04 976k 100k 196k c in : tdk c3225x7r2aa225m c out : avx 12063d106kat l1: cooper bussman sd25-330 load current (ma) 0 0 burst frequency (khz) 40 50 60 1 10 100 3630 ta04b 30 20 10 v in = 3.3v 20khz limit no limit v fb sw l1 22h v in run c out 22f v out 12v r1 200k c in 2.2f v in 12v to 65v fbo i set ss v prg1 v prg2 gnd LTC3630 r3 806k r4 10k c in : tdk c3225x7r2a225m c out : taiyo yuden emk316bj226ml-t l1:tdk slf7045470mr75 r2 14.3k 3630 ta05 input voltage (v) 10 0 maximum current (ma) 100 200 300 400 500 20 30 40 50 15 25 35 45 55 3630 ta05b 60 65 maximum load current maximum input current input current limit v out 2 ? r4 r3 + r4 maximum load current v in 2 ? r4 r3 + r4 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 22 3630f package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16(12)) 0911 rev c 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1.0 (.039) bsc 1.0 (.039) bsc 16 16 14 121110 1 3 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package variation: mse16 (12) 16-lead plastic msop with 4 pins removed exposed die pad (reference ltc dwg # 05-08-1871 rev c) www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 23 3630f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05 dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706 rev ?) www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3630 24 3630f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0512 ? printed in usa related parts typical application 4.5v to 65v input to 3.3v output, 1.5a regulator v out 3.3v 2.5a 3630 ta06 d1 l1 2.2h r osc 105k r ith 4.32k r1 105k c out : tdk c3225x5roj107m l2: vishay ihlp-2525cz-01 c in : murata gcm32dr72a225ka64l c1: tdk cga6p1x7r1c226m l1: coilcraft mss1048t-333 *LTC3630 only switches when v batt > 15v c vcc 1f c ith 1nf c out 100f sync/mode pgood rt ith v fb run track/ss pgnd intv cc pv in pv in boost sw sw sw pgnd pgnd ltc3603 r2 475k c bst 0.22f c fb 10pf v fb sw l1 33h v in run r1 200k c in 4.7f v in 4.5v to 65v fbo i set ss v prg1 v prg2 gnd LTC3630 r2 102k 22f part number description comments ltc3642 45v (transient to 60v) 50ma synchronous step-down dc/dc converter v in : 4.5v to 45v, v out(min) = 0.8v, i q = 12a, i sd = 3a, 3 3 dfn-8, msop-8 ltc3631 45v (transient to 60v) 100ma synchronous step-down dc/dc converter v in : 4.5v to 45v, v out(min) = 0.8v, i q = 12a, i sd = 3a, 3 3 dfn-8, msop-8 ltc3632 50v (transient to 60v) 20ma synchronous step-down dc/dc converter v in : 4.5v to 50v, v out(min) = 0.8v, i q = 12a, i sd = 3a, 3 3 dfn-8, msop-8 ltc3103 15v, 300ma synchronous step-down dc/dc converter with ultralow quiescent current v in : 2.5v to 15v, v out(min) = 0.6v, i q = 1.8a, i sd = 1a, 3 3 dfn-10, msop-10e ltc3104 15v, 300ma synchronous step-down dc/dc converter with ultralow quiescent current and 10ma ldo v in : 2.5v to 15v, v out(min) = 0.6v, i q = 2.6a, i sd = 1a, 4 3 dfn-14, msop-16e lt3970 40v, 350ma, 2.2mhz high efficiency micropower step-down dc/dc converter with i q = 2.5a v in : 4.2v to 40v, v out(min) = 1.21v, i q = 2.5a, i sd < 1a, 3 2 dfn-10, msop-10 lt3990 62v, 350ma, 2.2mhz high efficiency micropower step-down dc/dc converter with i q = 2.5a v in : 4.2v to 62v, v out(min) = 1.21v, i q = 2.5a, i sd < 1a, 3 3 dfn-10, msop-16e lt3971 38v, 1.2a, 2.2mhz high efficiency micropower step-down dc/dc converter with i q = 2.8a v in : 4.3v to 38v, v out(min) = 1.19v, i q = 2.8a, i sd < 1a, 3 3 dfn-10, msop-10e lt3991 55v, 1.2a, 2.2mhz high efficiency micropower step-down dc/dc converter with i q = 2.8a v in : 4.3v to 55v, v out(min) = 1.19v, i q = 2.8a, i sd < 1a, 3 3 dfn-10, msop-10e lt3682 36v, 60v max , 1a, 2.2mhz high efficiency micropower step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 75a, i sd < 1a, 3 3 dfn-12 ltc3891 low i q , 60v synchronous step-down controller v in : 4v to 60v, v out(min) = 0.8v, i q = 50a, i sd = 14a, 3 4 qfn-20, tssop-20e www.datasheet.co.kr datasheet pdf - http://www..net/

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